Testing 101: What is a BERT?

August 16, 2016

 

The term BERT stands for Bit Error Rate (or Ratio) Tester and refers to a class of test and measurement equipment that is used to transmit patterns (data) under specific conditions into a device under test (DUT) and then measure incoming data on its receiver where it compares if the received data matches what was originally transmitted. As such, a BERT consists of two main elements: a pattern generator where the data stream originates and an error detector which receives the incoming data.

 

The pattern generator can operate at many different data rates and the user can typically set both fixed pseudo-random bit sequences (PRBS) or user defined patterns. When the pattern sent from the pattern generator travels through the DUT and is received back at the error detector, a direct comparison can be made to determine if any of the bits of the pattern were received incorrectly (errors). This then allows for the computation of the ratio of correct to incorrect bits received at the error detector.

 

The increase in the speeds of various physical layer interfaces has created the need for different types of BERTs. Some are designed for us in lower speed testing, some for high speed testing, and others for parallel channel architectures. Additionally, there are also BERTs with the capability of adding stress or jitter onto the transmitted patterns which helps serve customers trying to verify the performance of receivers built into common high speed interfaces.

 

A specific of example of this type of measurement would be those looking to perform high speed receiver compliance testing of an interface like USB 3.0 or PCI Express. While there are separate standards bodies that govern the exact testing methodologies for these types of interfaces, the ultimate goal of the tests are similar: verify that the devices which utilize these technologies can properly receive incoming data under normal and stressful conditions. For example, a USB 3.0 port on your laptop has to be able to receive data from any USB 3.0 device.

 

Similarly, a PCI Express graphics card has to be able to receive data from any compatible motherboard that it may be installed in. By using a BERT to test these types of high speed receivers, an engineer can prove interoperability and compliance of the DUT to a specific standards document.

 

One last class of BERTs that is worth pointing out is the high speed category aimed at the testing of 100G and 400G Ethernet interfaces. The technology involved is typically a parallel architecture consisting of multiple lanes running a 25Gbps or 28Gbps, but may also include some advanced transmission techniques including pulse amplitude modulation or PAM-4.

 

This technology involves multi-level signaling where four distinct voltage levels can be used to encode two bits of data. This is different than traditional high speed digital signaling which uses two distinct voltage levels to encode one bit of data (called non-return to zero format or NRZ).

 

PAM-4 is being deployed now and there is a lot of focus on 32Gbaud (64 Gbps), 56Gbaud (112Gbps), and even 64 Gbaud (128 Gbps) implementations. The pattern generators in a BERT can generate a PAM-4 signal either by directly combing two signals together directly using power dividers or in a more sophisticated manner using a high performance digital to analog converter. Bit error ratio measurements of a PAM-4 signal is pretty difficult, however, as most BERTs still have traditional NRZ error detectors.

 

This means that multiple error detectors are required to be able to monitor the various voltage thresholds (three in total) simultaneously as well as an algorithm to properly compare the bits received to the bits transmitted.

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